Wideband Interference Suppression for Automotive mmWave CS Radar: From Algorithm-Based to Learning-Based ApproachesWANG Xiaoyan; KOIZUMI Ryoto; UMEHIRA Masahiro; SUN Ran; TAKEDA Shigeki, In recent times, there has been a significant focus on the development of automotive high-resolution 77GHz CS (Chirp Sequence) radar, a technology essential for autonomous driving. However, with the increasing popularity of vehicle-mounted CS radars, the issue of intensive inter-radar wideband interference has emerged as a significant concern, leading to undesirable missed targe detection. To solve this problem, various algorithm and learning based approaches have been proposed for wideband interference suppression. In this study, we begin by conducting extensive simulations to assess the SINR (Signal to Interference plus Noise Ratio) and execution time of these approaches in highly demanding scenarios involving up to 7 interfering radars. Subsequently, to validate these approaches could generalize to real data, we perform comprehensive experiments on inter-radar interference using multiple 77GHz MIMO (Multiple-Input and Multiple-output) CS radars. The collected real-world interference data is then utilized to validate the generalization capacity of these approaches in terms of SINR, missed detection rate, and false detection rate., The Institute of Electronics, Information and Communication Engineers
IEICE Transactions on Communications, 2024年12月01日
Stock Monitoring and Localization Systems for FIFO Method Using RFID Based Pressure Sensing Tag and AIDanang Kumara Hadi; Zequn Song; Budi Rahmadya; Ran Sun; Shigeki Takeda, This research introduces real-time monitoring and localizing product stock using the First-In-First-Out (FIFO) method with radio frequency identification (RFID) pressure sensing tags. The proposed FIFO system has RFID pressure sensing tags that detect pressure changes, generate sensor codes, and estimate a stock location. Integrating artificial intelligence (AI) improves location estimation accuracy of up-to-date stock visibility. The ability of RFID pressure sensing tags and AI to detect stock from sensor code data enables more effective asset management, optimizes stock management, reduces product waste, and contributes to better efficiency in product inventory management.
IEEJ Transactions on Electronics, Information and Systems, 2024年09月01日
An Auxiliary Antenna and Repeater Node for Reading Arrayed RFID Sensor Tags in Shielded AreasDanang Kumara Hadi; Zequn Song; Shusuke Kobayashi; Ran Sun; Budi Rahmadya; Shigeki Takeda, Collecting temperatures inside shield areas is a technological challenge for RFID sensor tags. This paper proposes a new RFID sensor tag reading technique inside shield areas such as metallic cases. The proposed method consists of an auxiliary antenna and repeater RFID sensor tag. A coaxial cable connects the repeater RFID sensor tag installed inside a shield area to the external auxiliary antenna. An RFID reader identifies multiple RFID sensor tags installed inside the shielded area through the repeater RFID sensor tag exploiting electromagnetic coupling effects. Experimental results using the chassis of a desktop computer validated that the proposed method identified the multiple RFID sensor tags and enabled measuring temperatures inside the metallic shield area.
2nd International Symposium on Information Technology and Digital Innovation: Creative Trends in Sustainable Information Technology Design and Innovation, ISITDI 2024, 2024年
Indoor Localization Based on Analyzing Observed Wi-Fi Access Point Logs Using ChatGPTBudi Rahmadya; Yuta Sato; Shigeki Takeda; Ran Sun; Zequn Song; Danang Kumara Hadi, Argent demands regarding indoor real-time localization systems (RTLS) accelerate research and developments on these technologies. Recent advances in Wi-Fi technologies, including Wi-Fi 6 and 7, further facilitate the development of RTLS technologies by utilizing signal processing and artificial intelligence/machine learning (AI/ML) technologies. These research and development activities also accelerate future wireless communication for achieving the integrated sensing and communication (ISAC) concept. The recent developments in Wi-Fi technologies have led to increased numbers of APs for gaining reliable wireless links. Therefore, we observe many APs in workplaces, office environments, and homes. These situations enable exploiting observed Wi-Fi information for localizations. This paper proposed an indoor localization method based on the analyses of surrounding Wi-Fi access points using ChatGPT. The experiments validated that ChatGPT could infer the corresponding room names to given unknown Wi-Fi logs based on analyzing known Wi-Fi logs observed in priori in individual rooms.
2nd International Symposium on Information Technology and Digital Innovation: Creative Trends in Sustainable Information Technology Design and Innovation, ISITDI 2024, 2024年
Experimental Evaluations on Learning-based Inter-radar Wideband Interference Mitigation Method
Ryoto Koizumi; Xiaoyan Wang; Masahiro Umehira; Ran Sun; Shigeki Takeda
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2024年01月, ［査読有り］
A Stray Read Suppression Method in UHF passive RFID Systems Utilizing a Metal Plate
H. Arai; S. Takeda; R. Sun, ラスト(シニア)オーサー
IEEJ Trans. on C, 2023年08月, ［査読有り］
24GHz帯FMCWレーダーによる河川水位測定
孫冉; 武田茂樹; 桑原祐史; 小林薫
電気学会論文誌C, 2023年08月, ［査読有り］
A Higher Angular Resolution Millimeter-Wave Automotive Radar Utilizing an Antenna Element Space Pseudo Peak Suppression
K. Suzuki; Y. Owada; R. Sun; S. Takeda; M. Umehira; and H. Kuroda
Smart City Workshop 2022 (sponsored by IEEJ), CMN-22-016, March 2022., 2022年03月
A Higher Angular Resolution Millimeter-Wave Automotive Radar Utilizing an Antenna Element Space Pseudo Peak Suppression to Identify Obstacles on a Road
Y. Owada; K. Suzuki; R. Sun; S. Takeda; M. Umehira; and H. Kuroda
Smart City Workshop 2022 (sponsored by IEEJ), CMN-22-018, March 2022., 2022年03月
A Link Analysis Based Device-Free Localization Method of RFID Tags Using a Tiny Drone having a Wound-Wire for Shadowing Propagation Paths
B. Rahmadya; S. Takeda; R. Sun
Smart City Workshop 2022 (sponsored by IEEJ), CMN-22-020, March 2022., 2022年03月
RFID Tag Antenna Design for Books and Document Management Applications Considering the Surrounding Paper
R. Miyajima; B. Rahmadya; S. Takeda; R. Sun
Smart City Workshop 2022 (sponsored by IEEJ), CMN-22-022, March 2022., 2022年03月
A Stray Reads Suppression Method of UHF Passive RFID tags Utilizing the Image Theory
H. Arai; S. Takeda; R. Sun
Smart City Workshop 2022 (sponsored by IEEJ)CMN-22-023, March 2022, 2022年03月
A Battery-Less RFID-Based Wireless Vibration and Physical-Shock Sensing System Using Edge Processing for Long-Term Measurements
Z. Song; R. Sun; B. Rahmadya; S. Takeda, IEEE
2021 31st International Telecommunication Networks and Applications Conference (ITNAC), Nov. 2021., 2021年11月, ［査読有り］
Visual management of medical things with an advanced color-change RFID tag, (2021).
Sun; R.; Rahmadya; B.; Kong; F. Takeda. S., ラスト(シニア)オーサー
Sci. Rep., 2021年11月, ［査読有り］
M字形誘電体アレー構造による広帯域移相器
孫冉; 武田茂樹; 鹿子嶋憲一
電気学会論文誌C, vol.141, no. 8, 2021年08月, ［査読有り］
複数通信事業者及び通信方式に対する屋内基地局アンテナ配置及び配線設計の一手法
佐藤義人; 武田茂樹
電気学会論文誌C, vol.141, no. 8,, 2021年08月, ［査読有り］
Antenna Element Space Interference Cancelling Radar for Angle Estimations of Multiple Targets
R. Sun; J. Sakai; K. Suzuki; J. Zheng; S. Takeda; M. Umehira; X. Wang; and H. Kuroda
IEEE Access, vol. 9, pp. 72547-72555, 2021年05月, ［査読有り］
Proposal of Antenna Element Space Interference Cancelling Radar.
R. Sun; J. Sakai; K. Suzuki; J. Zheng; S. Takeda; M. Umehira; H. Kuroda
Smart City Symposium 2021 (sponsored by IEEJ), CMN-21-021, pp.21-23, March 2021., 2021年03月
Virtually Extended Array Antennas with an Overlearning Supression for Automotive mm-Wave radars
J. Sakai; K. Suzuki; J. Zheng; R. Sun; S. Takeda; M. Umehira; H. Kuroda
Smart City Symposium 2021 (sponsored by IEEJ), CMN-21-025, pp.41-44, March 2021., 2021年03月
A framework to determine secure distances for either drones or robots based inventory management systems,
B. Rahmadya; R. Sun; S. Takeda; K. Kagoshima; M. Umehira, 責任著者, IEEE
IEEE Access, 2020年09月, ［査読有り］
Inter-radar Interference Analysis of FMCW radars with Different Chirp Rates
Yuya Makino; Takuya Nozawa; Masahiro Umehira; Xiaoyan Wang; Shigeki Takeda; Hiroshi Kuroda
Journal of Engineering, 2019年10月, ［査読有り］
A Proposal of Multiple Access FMCW Radar for Inter-radar Interference Avoidance
Mikihiro Kurosawa; Takuya Nozawa; Masahiro Umehira; Xiaoyan Wang; Shigeki Takeda; Hiroshi Kuroda
Journal of Engineering, 2019年10月, ［査読有り］
Secure Distances Between a Drone and an RFID-Tag-Afixed Metallic Object for Automated Inventory Management Systems in Warehouses
B. Rahmadya; S. Takeda; K. Kagoshima; M. Umehira
2019 IEEJ Smart City Syposium, 2019年10月, ［査読有り］
A feasibility study on the safety confirmation system using NFC and UHF band RFID tags
S. Takeda; K. Kagoshima; M. Umehira, 筆頭著者
IEICE Transactions on Information and Systems, 2019年09月, ［査読有り］
Experimental validation of a new measurement metric for radio-frequency identification-based shock-sensor systems
X. Chen; D. Feng; S. Takeda; K.Kagoshima; M. Umehira, 責任著者
IEEE Journal of Radio Frequency Identification, 2018年12月, ［査読有り］
A Yagi-Uda antenna-based RFID tag for books and documents management applications
Y. Takagi; S. Takeda; K. Kagoshima; M. Umehira
2018 ISAP, 2018年10月24日, ［査読有り］
Measurement of a novel UHF RFID based battery-less vibration frequency sensing tag
D. Feng; T. Higuchi; Y. Kobayashi; S. Takeda; K. Kagoshima; M. Umehira
2018 ISAP, 2018年10月24日, ［査読有り］
Energy efficient learning-based indoor multi-band WLAN for smart buildings
X. Wang; M. Umehira; H. Otsu; T. Kawatani; S. Takeda
IEEE Access, 2018年06月, ［査読有り］
バッテリーレスUHF帯無線傾斜/振動センサタグの提案
小林有理; 馮東方; 武田茂樹; 鹿子嶋憲一; 梅比良正弘
土木学会論文集F3(土木情報学), 2017年03月, ［査読有り］
移動体通信用逆L型プローブ給電水平偏波無指向性アンテナ
清水隆行; 鈴木貴之; 武田茂樹; 鹿子嶋憲一; 梅比良正弘
信学論B, 2016年09月01日, ［査読有り］
UHF帯RFIDによる災害電子掲示板に関する検討
宮坂隆平; 武田茂樹; 鹿子嶋憲一; 梅比良正弘
土木学会論文集F3(土木情報学), 2016年03月, ［査読有り］
Improving Performance by Countering Human Body Shadowing in 60 GHz Band Wireless Systems by Using Two Transmit and Two Receive AntennasT. Nagayama; S. Takeda; M. Umehira; K. Kagoshima and T. Miyajima, This paper proposes the use of two transmit and two receive antennas spaced at roughly the width of a human body to improve communication quality in the presence of shadowing by a human body in the 60 GHz band. In the proposed method, the transmit power is divided between the two transmit antennas, and the receive antenna that provides the maximum receive level is then chosen. Although the receive level is reduced by 3 dB, the maximum attenuation caused by human body shadowing is totally suppressed. The relationship between the antenna element spacing and the theoretical spacing based on the 1st. Fresnel zone theory is clarified. Experiments confirm that antenna spacing several centimeters wider than that given by the 1st. Fresnel zone theory is enough to attain a significant performance improvement., IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
IEICE Trans. on Commun., 2016年02月
Investigation on the reactance loading and EM coupling feed for a design of a dual frequency planar antennaK. Kagoshima; M. Uchida; S. Takeda; M. Umehira, We investigate the design method for a compact antenna composed of an exciting loop and parasitic loops which are electromagnetically con pled for a dual frequency operation. First, we presented a useful formula for determining the reactance load which makes the parasitic loop to be resonant or nearly resonant. Electromagnetic coupling mechanism were analyzed by using impedance matrix between antenna elements and design formulas for adjusting impedance matrix elements were also presented. Based on the presented formulas, the prototype planar antenna printed on a FR-4 PCB was fabricated and the comparison between calculated and measured results ensured the validity of the design method., IEEE
PROCEEDINGS OF THE 2016 IEEE-APS TOPICAL CONFERENCE ON ANTENNAS AND PROPAGATION IN WIRELESS COMMUNICATIONS (APWC), 2016年,
［査読有り］ Feasibility of RSSI based 60 GHz WLAN discovery for multi-band WLAN
S. Wada; M. Umehira; S. Takeda; T. Miyajima; K. Kagoshima
IEICE Communications Express, 2015年05月, ［査読有り］
A Frequency Cooperative ARQ Scheme for Multi-band WLAN
T. Motegi; S. Koike; T. Miyajima; M. Umehira; S. Takeda; K. Kagoshima
IEICE Communications Express, 2015年02月, ［査読有り］
モータ固定子内部で発生する絶縁不良箇所検出に関する検討
中山健一; 松竹由佳里; 柳澤隆久; 武田茂樹; 鹿子嶋憲一; 梅比良正弘
電気学会論文誌A, 2014年02月, ［査読有り］
ブリッジサセプタンスと伝送線路を組み合わせた3素子MIMOアンテナ用簡易デカップリング回路の設計法の提案
遠藤直之; 鹿子嶋憲一; 武田茂樹
信学論 B, 2014年01月
書籍に埋め込まれた2.45GHz帯RFIDタグの放射特性に関する検討,
内田涼仁; 増田大輝; 武田茂樹; 鹿子嶋憲一; 梅比良正弘
信学論B, 2013年11月, ［査読有り］
近接配置基地局アレーアンテナの相互結合抑圧法
西村一輝; 金澤潤; 鹿子嶋憲一; 武田茂樹
信学論B, 2012年11月, ［査読有り］
有限長金属筒構造利用による金属円筒裏面のRFIDタグ読み取り性能向上方法の提案
大鷲祐貴; 伊藤隆広; 内田涼仁; 武田茂樹; 鹿子嶋憲一; 梅比良正弘
信学論B, 2012年09月, ［査読有り］
書籍に貼り付けた2.45GHz帯RFIDタグの同時読み取り時に発生するデッドスポットに関する評価
内田涼仁; 武田茂樹; 鹿子嶋憲一
信学論B, 2012年03月, ［査読有り］
A Cross Polarization Suppressed Sequential Array with L-Probe Fed Rectangular Microstrip AntennasK. Ikeda; K. Sato; K. Kagoshima; S.Obote; A. Tomiki; T. Toda, In this paper, we present a sequentially rotated array antenna with a rectangular patch MSA fed by an L-probe. Since it's important to decrease couplings between patch elements in order to suppress the cross-polarization level, rectangular patches with aspect ratio of k are adopted. We investigate the cross-polarization level of the sequential array and discuss the relationship between the cross-polarization level and the mutual coupling. As a result, the bandwdith of the antenna element is obtained 14.6% when its VSWR is less than 1.5, and the directivity and cross-polarization level of a 4-patch sequential array are 10.8 dBic and 1.7 dBic, respectively, where k=0.6 and the patch spacing of d=0.5 wave length. These characteristics are 5.6 dB and 5.8 dB better than the corresponding values of a square patch sequential array antenna., IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
IEICE Trans. on Commun., vol.E94-B, no.9, pp.2653-2655, 2011年09月
2.45 GHz 帯パッシブRFID タグの背後に金属が存在する場合のデッドスポットに関する解析
王鵬; 鄭純; 山田祥; 尾保手茂樹; 鹿子嶋憲一
信学論B, vol.J93-B, no.11, pp.1531-1540, 2010年11月, ［査読有り］
折返し逆L 形プローブ給電により帯域拡大したパッチアンテナ
池田一樹; 鹿子嶋憲一; 尾保手茂樹
信学論B, 2010年03月, ［査読有り］
Reading Technique of 2.45GHz Band Small RFID Tags with an AdapterP. Wang; H. Koga; S. Yamada; S. Obote; K. Kagoshima and K. Araki, A 2.45-GHz-band small passive radio-frequency identification (RFID) tag consists of a small loop antenna and chip, and its size is several millimeters. Because of the tag's poor impedance-matching characteristic and radiation efficiency, an ordinary reader has difficulty reading it. We propose a new technique for reading the tag that involves installing a square half-wavelength meander-line conductor on the reader as an adapter and placing the adapter in the vicinity of the tag, and verify the effectiveness of the technique by simulation and experiment. Moreover, characteristics of simultaneous read of the small RFID tags by the proposed reading technique are revealed by simulation and experimental results., IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
IEICE Trans. Fundamentals. Vol.E92A, no.11, pp.2851-2857, 2009年11月,
［査読有り］ 金属板近傍における2.45GHz帯パッシブRFIDタグの読み取り距離に関する検討
王鵬; 荒木大二郎; 尾保手茂樹; 鹿子嶋憲一; 松本典剛; 荒木憲司
電気学会論文誌, 2009年07月, ［査読有り］
受信アレーアンテナの素子整合負荷決定法
鹿子嶋憲一; 田中崇行; 尾保手茂樹; 市川佳弘
信学論B, 2007年05月
Performance study of DOA-based indoor location positioning utilizing MIMO wireless LAN system
A. Hafiizh; F. Imai; M. Minami; K. Ikeda; S. Obote; K. Kagoshima
ISAP 2006, Singapore (CD-ROM), 2006年11月
A study on frame synchronization method for adaptive array antenna
S. Obote; Y. Ichikawa; K. Kagoshima
Proceeding of APS2006, 2006年07月, ［査読有り］
Dual-mode space-temporal simultaneous processing equalizerY. Ichikawa; S. Obote; and K. Kagoshima, A tapped delayed line adaptive array antenna (TDL-AAA) and a space-temporal simultaneous processing equalizer (ST-SPE) are proposed as simple space-temporal equalizers based on minimum mean square error (MMSE) criterion. The ST-SPE has a compact hardware with a small number of taps compared to that of the TDL-AAA. The ST-SPE can reduce the computational complexity of the space-temporal joint equalization and it works effectively under the minimum phase condition such as appeared at line-of-sight (LOS) propagation environments at a high antenna height base station. However the ST-SPE cannot work under a non-minimum phase condition caused under N-LOS (non-line-of-sight). On the other hand, the TDL-AAA whose reference signal is synchronized at the center tap (TDL-AAA(C)) can work even in the non-minimum phase condition. In this paper, we propose a dual-mode space-temporal simultaneous processing equalizer (Dual-mode ST-SPE) which has a simple configuration and also works in non-minimum phase condition. The Dual-mode ST-SPE can reduce the computational complexity compared to the TDL-AAA(C)., SPRINGER
Kluwer Academic Publishers, Wireless Personal Communications, 2005年12月
Study on the design of maximum directivity of a receiving array with mutual coupling
K. Kagoshima; S. Obote; Y. Ichikawa; M. Yamane
Proceeding of ISAP2005, Seoul, Korea, 2005年08月
Pattern synthesis of and array antenna with maximum directivity and nulls at specified directionsK. Kagoshima; S. Obote; Y. Ichikawa; M. Yamane; and T. Tanaka, In order to solve a problem of maximizing a directivity of a transmitting array antenna with nulls at specified directions, we intended to utilize an adaptive. antenna algorithm which enables the SNR to be maximum under the incidence of interferences. However, we encountered the discrepancy between transmitting antenna patterns and receiving ones. We investigated why this discrepancy arises, although a reciprocity theorem is effective between the transmitting pattern and the receiving one. Through these investigations, we derived the equation which determines the matched load impedances of the array elements and solved it numerically up to five elements. We also derived an equation to evaluate output voltages which are summed up into an output of the array and confirmed the coincidence between the transmitting pattern and the receiving one., IEEE
Fifth Int. Conf. on Antenna Theory and Techniques (ICATT '05), in Kiev, Ukraine, 2005年05月
PCカードスロットに完全収納できる無線LAN用アンテナ
石田淳; 藤枝重雪; 鹿子嶋憲一; 尾保手茂樹
信学論B, 2004年10月
適応信号処理の基礎と応用[III] －適応アレー信号処理－
尾保手茂樹; 市川佳弘; 鹿子嶋憲一
信学誌, 2003年10月
MMSE-SMIアダプティブアレーアンテナにおける周波数オフセット補償法
市川佳弘; 尾保手茂樹; 鹿子嶋憲一
信学論B, 2003年09月
多層プリント基板電源・グランド層の共振周波数特性の解析
中山健一; 鹿子嶋憲一; 尾保手茂樹
信学論B, 2003年06月
A computation reduced MMSE adaptive array antenna using space-temporal simultaneous processing equalizerY. Ichikawa; K. Tomitsuka; S. Obote; and K. Kagoshima, When we use an adaptive array antenna (AAA) with the minimum mean square error (MMSE) criterion under the multipath environment, where the receiving signal level varies, it is difficult for the AAA to converge because of the distortion of the desired wave. Then, we need the equalization both in space and time domains. A tapped-delay-line adaptive array antenna (TDL-AAA) and the AAA with linear equalizer (AAA-LE) have been proposed as simple space-temporal equalization. The AAA-LE has not utilized the recursive least square (RLS) algorithm. In this paper, we propose a space-temporal simultaneous processing equalizer (ST-SPE) that is an AAA-LE with the RLS algorithm. We proposed that the first tap weight of the LE should be fixed and the necessity of that is derived from a normal equation in the MMSE criterion. We achieved the space-temporal simultaneous equalization with the RLS algorithm by this configuration. The ST-SPE can reduce the computational complexity of the space-temporal joint equalization in comparison to the TDL-AAA. when the ST-SPE has almost the same performance as the TDL-AAA in multipath environment with minimum phase condition such as appeared at line-of-sight (LOS)., IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
IEICE Trans. on Commun., 2002年12月
時間差サンプリングアダプティブアレーアンテナ
市川佳弘; 富塚浩志; 尾保手茂樹; 鹿子嶋憲一
信学論B, 2002年12月
QPSK復調における周波数オフセット推定法
尾保手茂樹; 鹿子嶋憲一
信学論A, 2002年11月
MMSE adaptive array antenna with dual-mode space temporal simultaneous processing equalizer
Y. Ichikawa; S. Obote; K. Kagoshima
Proc. of ISAP-i02, Yokosuka, Japan, 2002年11月
Characteristics of the radiated emission from a multiplayer PCB with a slit
K. Nakayama; K. Kagoshima; S. Obote
Proc. of ISAP-i02, Yokosuka, Japan, 2002年11月
Computational complexity reduced MMSE adaptive array antenna with space-temporal joint equalization
Y. Ichikawa; K. Tomitsuka; S. Obote; K. Kagoshima
Proceedings of APCC2001,, 2001年09月
Computational complexity reduced MMSE adaptive array antenna with space-temporal joint equalization
Y. Ichikawa; K. Tomitsuka; S. Obote; K. Kagoshima
Proceedings of IEEE 2001 AP-S International Symposium, 2001年06月
The automatic counting of Chlorella using image processing and neural networkY. Sumi; M. Ota; N. Yabuki; S. Obote; Y. Matsuda; and Y. Fukui, In the culture of marine chlorellas. it is necessary to count the number in order to understand the condition of Increase. For that propose, counting by the naked eye using the microscope has been used. However; this method requires a lot of time and work. We have developed the automatic chlorella counter using image processing and neural network. Its effectiveness is confirmed through the experiment., IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
IEICE Trans. Fundamentals, 2001年03月
Robust DSP type squaring loop with adaptive notch filter type frequency estimator and adaptive BPFS. Obote; Y. Sumi; Y. Itoh; Y. Fukui; and M. Kobayashi, Recently, in the modem, the spread spectrum communication system and the software radio, Digital Signal Processor type Squaring Loop (DSP-squaring-loop) is employed in the demodulation of Binary Phase Shift Keying (BPSK) signal. The DSP-squaring-loop extracts the carrier signal that is used for the coherent detection. However, in case the Signal to Noise Ratio (SNR) is low, the DSP-Phase Locked Loop (DSP-PLL) can not pull in the frequency offset and the phase offset. In this paper, we propose a DSP-squaring-loop that is robust against noise and which uses the adaptive notch filter type frequency estimator and the adaptive Band Pass Filter (BPF). The proposed method can extract the carrier signal in the low SNR environment. The effectiveness of the proposed method is confirmed by the computer simulation results., IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
IEICE Trans. Fundamentals, 2001年02月
A noise reduction method using adaptive notch filter
S. Obote; M. Kobayashi
Proceedings of ISPACS2000, 2000年11月
Automatic counting method of number of Chlorella using neural network
M. Ota; Y. Sumi; N. Yabuki; S. Obote; Y. Matsuda; Y. Fukui
Proceedings of ISPACS2000, 2000年11月
Prescaler PLL frequency synthesizer with the gate controller system（GCS）introduced to the multi-programmable divider method
Y. Sumi; H, Ishii; S. Obote; N. Kitai; Y. Fukui
Proceedings of ISPACS2000, 2000年11月
A study on the automatic counting method of number of Chlorella
M. Ota; Y. Sumi; N. Yabuki; S. Obote; Y. Matsuda; Y. Fukui
Proceedings of ITC-CSCC 2000, 2000年07月
PLL frequency synthesizer using binary phase comparison
S. Obote; Y. Sumi; N. Kitai; Y. Fukui; Y. Itoh
IEICE Trans., 2000年03月
PLL frequency synthesizer with multi-programmable dividerY. Sumi; S. Obote; N. Kitai; H. Ishii; R. Furuhashi; and Y. Fukui, The lock-up time of a PLL frequency synthesizer depends on each loop gain. In this paper, we pay attention to the gain of a programmable divider which is one of the important elements of PLL, and propose a new method for improving the gain of programmable divider. In order to achieve the increase in gain of the programmable divider, we propose a new PLL frequency synthesizer with multi-programmable divider by which the gain is increased even when the same reference frequency and the same division ratio as usual are used. It will be shown by the theoretical considerations and experimental results that a higher speed lock-up time can be achieved., IEEE
IEICE Trans., 2000年03月
PLL frequency synthesizer with multi-programmable divider
Y. Sumi; S. Obote; N. Kitai; H. Ishii; R. Furuhashi; Y. Fukui
IEICE Trans., 2000年03月
A novel (N+1/2)pulse swallow programmable divider for the prescaler PLL frequency synthesizerS. Obote; Y. Sumi; K. Syoubu; and Y. Fukui, In this paper, we propose a new speedup method of frequency switching time of the prescaler PLL frequency synthesizer using (N + 1/2) pulse swallow programmable divider. The (N + 1\2) pulse swallow programmable divider can set half the division ratio (D\2) in comparison with the desired division ratio D. In the improved prescaler method, since the total division ratio including (1\2) fixed prescaler becomes desired division ratio D, the reference frequency which is two times bigger than that of the conventional prescaler method can be used. Therefore, the loop gain, the natural angular frequency and the damping factor are increased, and the frequency switching time can be speeded up. By the experimental results, it is observed that the frequency switching time of the improved prescaler method is two times faster than that of the conventional prescaler method., KLUWER ACADEMIC PUBL
Analog integrated circuits and signal processing, Kluwer academic publishers, 1999年11月
A digital signal precessing type frequency locked loop for frequency shift keying demodulationS. Obote; Y. Sumi; K. Syoubu; Y. Itoh; and Y. Fukui, In this paper, we propose a digital signal processing type frequency locked loop (DSP-FLL) using a frequency difference detector (FDD). Since the DSP-FLL is controlled by the frequency, the pole of the voltage controlled oscillator vanishes in the baseband equivalent circuit. Therefore, the transfer function becomes first order and a ringing does not occur. Furthermore, it can be understood from the detection property of the FDD that a cycle slip does not occur and the DSP-FLL can pull in the frequency step input up to half of the sampling frequency., TAYLOR & FRANCIS LTD
International journal of electronics, 1999年11月
A virtual prescaler PLL frequency synthesizer by multi-programmable divider
Y. Sumi; S. Obote; N. Kitai; H. Ishii; R. Furuhashi; Y. Itoh; Y. Fukui
Proc. The 10th International Symposium on Personal Indoor and Mobile Radio Communication (PIMRC), Asia and Pacific Trade Center, Osaka, Japan, 1999年09月
PLL synthesizer with multi-programmable divider and multi-phase detectorY. Sumi; S. Obote; N. Kitai; H. Ishii; and R. Furuhashi, In this paper, we first propose the prescaler-type PLL frequency synthesizer with multi-programmable divider and multi-phase detector for the speedup of lock up time. We next propose the reduction method of the number of programmable dividers by introducing the (N+1/2) programmable divider., IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
IEEE Trans. Consumer Electronics, 1999年08月
PLL frequency synthesizer for clock generator of digital signal processor using (N+1/2) programmable divider
S. Obote; Y. Sumi; N. Kitai; H. Ishii; Y. Fukui; Y. Itoh
Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Island of Sado, Japan, 1999年07月
A study on multi-fold method in PLL frequency synthesizer
Y. Sumi; S. Obote; N. Kitai; R. Furuhashi; H. Ishii; Y. Fukui; Y. Itoh
Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Island of Sado, Japan, 1999年07月
PLL synthesizer with multi-programmable divider and multi-phase detector
Y. Sumi; S. Obote; N. Kitai; H. Ishii; R. Furuhashi
Digest IEEE International Conference on Consumer Electronics (ICCE), 1999年06月
A new prescaler PLL frequency synthesizer with multi-programmable divider
Y. Sumi; S. Obote; N. Kitai; R. Furuhashi; H. Ishii; Y. Itoh; Y. Fukui
Proc. 3rd Analog VLSI Workshop, Taipei, Taiwan, 1999年05月
Prescaler PLL frequency synthesizer introducing multi-(N+1/2) programmable divider
Y. Sumi; S. Obote; N. Kitai; H. Ishii; R. Furuhashi; Y. Itoh; Y. Fukui
Proc. 3rd Analog VLSI Workshop, Taipei, Taiwan, 1999年05月
Performance improvement in a binary phase comparator type PLL frequency synthesizerS. Obote; Y. Sumi; N. Kitai; Y. Fukui; and Y. Itoh, In a phase locked loop (PLL) frequency synthesizer with binary phase comparator, ringing is hard to be suppressed. In this paper, we proposed the PLL frequency synthesizer with modified binary phase comparator which can solve the above problem. The effectiveness of the proposed method will be confirmed by PSpice simulation results., IEEE
Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, USA, 1999年05月
PLL frequency synthesizer with auxiliary programmable dividerY. Sumi; S. Obote; N. Kitai; R. Furuhashi; Y. Matsuda; and Y. Fukui, The lock-up time of a PLL frequency synthesizer depends on each loop gain. In this paper, we pay attention to the gain of a programmable divider which is one of the important elements of PLL, and propose a new method for improving the gain of programmable divider. In order to achieve the increase in the gain of the programmable divider, we already proposed a new PLL frequency synthesizer with multi-programmable divider by which the gain is increased even when the same reference frequency and the same division ratio as usual are used. In this paper we propose a simple PLL frequency synthesizer with an auxiliary programmable divider which is suitable for LSI implementation. It will be shown by the theoretical considerations and experimental results that a higher speed lock-up time can be achieved., IEEE
Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, USA, 1999年05月
Dead-zone-less PLL frequency synthesizer by hybrid phase detectorY. Sumi; S. Obote; N. Kitai; R. Furuhashi; H. Ishii; Y. Matsuda; and Y. Fukui, In this paper, in order to achieve the low phase noise in a PLL frequency synthesizer, we propose a new dead-zone-less PLL frequency synthesizer by hybrid phase detectors. We have developed the combination divider with (N+1/2) programmable divider and (1/2) fixed divider and the 90 degrees shift circuit and developed hybrid phase detectors method with both the exclusive-OR type phase detector and the normal frequency-phase detector. The former detector requires the two input signals with 50% duty factor and pi/2 phase difference under the locked state. A (N+1/2) programmable divider with a (1/2) fixed divider and the 90 degrees phase shifter are effectively employed to meet the above conditions. Both the simulation and experimental results show that the proposed synthesizer works successfully., IEEE
Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Orlando, USA, 1999年05月
Speed up of frequency switching time in PLL frequency synthesizers using a target frequency detectorS. Obote; Y. Sumi; N. Kitai; K. Syoubu; Y. Fukui; and Y. Itoh, In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time T-a for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At T-a, the programmable divider, the reference divider and the phase comparator are reset, and the phase of the PLL frequency synthesizer is initialized and the phase synchronization is achieved. In the proposed method, since the ringing in the transient state does not occur, the output of the PLL frequency synthesizer converges to the target frequency at T-a and the frequency switching time is speeded up. The effectiveness of the proposed method will be confirmed by experimental results., IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
IEICE Trans. Fundamentals, 1999年03月
PLL frequency synthesizer with multi-phase detectorY. Sumi; K. Syoubu; S. Obote; Y. Fukui; and Y. Itoh, The lock-up time of a PLL frequency synthesizer mainly depends on the total loop gain. Since the gain of the conventional phase detector is constant, it is difficult to improve the lock-up time by the phase detector. In this paper, we reconsider the operation of the phase detector and propose the PLL frequency synthesizer with multi-phase detector in which the gain of phase detector is increased by using four stage phase detectors and charge pumps. Then,a higher speed lock-up time and good spurious characteristics cab be achieved., IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
IEICE Trans. Fundamentals, 1999年03月
PLL frequency synthesizer system utilizing multi-programmable dividers
Y. Sumi; K. Syoubu; S. Obote; Y. Fukui; Y. Itoh
Proc. European Signal Processing Conference (EUSIPCO), Island of Rhodes, Greece, 1998年09月
DSP-FLL for FSK demodulation
S. Obote; Y. Sumi; K. Syoubu; Y. Itoh; Y. Fukui
Proc. European Signal Processing Conference (EUSIPCO), Island of Rhodes, Greece, 1998年09月
A new PLL frequency synthesizer using multi-programmable dividerY. Sumi; K. Syoubu; S. Obote; Y. Fukui; and Y. Itoh, In this paper, we propose a new Phase Locked Loop (PLL) frequency synthesizer utilizing the multi-programmable divider which can;attain a higher speed lock-up time by increasing the loop gain. The effectiveness of the PLL frequency synthesizer with the multi-programmable divider will be shown by theoretical considerations and experimental results., IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
IEEE Trans. Consumer Electronics, 1998年08月
PLL frequency synthesizer with multi-loop method
Y. Sumi; K. Syoubu; S.Obote; Y. Fukui; Y. Itoh
Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Sokcho, Korea, 1998年07月
Speedup of frequency switching time in PLL frequency synthesizers utilizing a target frequency detector
S. Obote; Y. Sumi; N. Kitai; K. Syoubu; Y. Fukui; Y. Itoh
Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Sokcho, Korea, 1998年07月
Speedup of frequency switching time in PLL frequency synthesizers using the target frequency detector
S. Obote; Y. Sumi; N. Kitai; K. Syoubu; Y. Fukui; Y. Itoh
Proc. 2nd Analog VLSI Workshop, Santa Clara, USA, 1998年06月
Multi-loop PLL frequency synthesizer
Y. Sumi; K. Syoubu; S. Obote; Y. Fukui; Y. Itoh
Proc. 2nd Analog VLSI Workshop, Santa Clara, USA, 1998年06月
Dual loop DSP-PLL with wide frequency acquisition range and fast frequency acquisitionS. Obote; Y. Sumi; K. Syoubu; Y. Fukui; and Y. Itoh, In this paper, we propose a new Dual Loop Digital Signal Processing type Phase Locked Loop (Dual Loop DSP-PLL) using Digital Signal Processing type Frequency Locked Loop (DSP-FLL) which we propose and the first order TAN type DSP-PLL (TAN-DSP-PLL). It is confirmed by the simulation results that Dual Loop DSP-PLL can pull in the frequency without cycle slip up to half of the sampling frequency. Moreover, the frequency acquisition time is faster and phase variance is smaller than those of the second order TAN-DSP-PLL. Therefore, the performance of the proposed Dual Loop DSP-PLL is superior to conventional DSP-PLLs., IEEE
Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Monterey, USA,, 1998年05月
On the Speedup of Lock up Time in the Frequency SynthesizerY. Sumi; S. Obote; K. Tsuda; K. Syoubu; and Y. Fukui, A new speed-up method of lock up time is proposed for the phase locked loop (PLL) frequency synthesizer in the local oscillation circuit of a radio receiver. Doubling of reference frequency is achieved by using a new (N+1/2) programmable divider which enables a half division ratio, compared with that of a conventional divider, and it leads to a bigger loop gain K and the speed-up of lock up time. The experimental results of lock up time will be given together with the spectrum of the output frequency., TAYLOR & FRANCIS LTD
International Journal of Electronics, 1998年02月
A New Fractional-N PLL Frequency Synthesizer
Y. Sumi; S. Obote; Y. Fukui; K. Tsuda; K. Syoubu
The Journal of Circuits, Systems and Computers, 1998年
Fast Settling PLL Frequency Synthesizer Utilizing the Frequency Detector Method Speedup CircuitY. Sumi; S. Obote; K. Narai; K. Tsuda; K. Syoubu; and Y. Fukui, In this paper, we propose the fast frequency settling Phase Locked Loop (PLL) frequency synthesizer utilizing the Frequency Detector Method Speedup Circuit (FDMSC). FDMSC is composed of a Frequency Detector (FD) and a Charge Controller (CC). By CC, the control voltage of Voltage Controlled Oscillator (VCO) is forced to move to the objective value, and once the objective frequency is detected by FD, FDMSC can suppress the transient response of a PLL frequency synthesizer. The effectiveness of the proposed PLL frequency synthesizer is shown through some experiments., I E E E
IEEE Transaction Consumer Electronics, 1997年08月
PLL frequency synthesizer with multi-phase detector
Y. Sumi; K. Syoubu; K. Tsuda; S. Obote; Y. Fukui
Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Okinawa, Japan, 1997年07月
Improvement of the prescaler method by the (N+1/2) pulse swallow type PLL frequency synthesizer
Y. Sumi; Y. Tanimoto; K. Tsuda; S. Obote; K. Syoubu; Y. Fukui
Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Okinawa, Japan, 1997年07月
Speedup of lock up time in the PLL frequency synthesizer using frequency detectorY. Sumi; S. Obote; K. Narai; K. Tsuda; K. Syoubu; and Y. Fukui, In this paper, we propose a new speedup method of lock up time in the Phase Locked Loop (PLL) frequency synthesizer which is used in the automatic tuning instruments of the radio receiver. When a division ratio of the programmable divider is changed, PLL frequency synthesizer shows the transient response of the second order system. Therefore, the PLL frequency synthesizer can not help having a slow lock up time. For the improvement of the lock up time, first, in order to find objective frequency, we propose a new frequency detector (FD) which detects only the frequency agreement between the reference frequency fr and feedback one fv. Once the frequency agreement is detected, the reference divider and programmable divider are reset and the phase between the reference frequency fr and feedback one fv is forced to be locked. Moreover, the input of charge pump is kept same state by Charge Controller (CC) during the change of the division ratio to the frequency agreement. As a result, the speedup of lock up time can be achieved by adopting the FD and CC at the same time., I E E E
Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Hong Kong, 1997年06月
Fast settling PLL frequency synthesizer utilizing the frequency detector method speedup circuitY. Sumi; S. Obote; K. Narai; K. Tsuda; K. Syoubu; and Y. Fukui, In this paper, we propose the fast frequency settling Phase Locked Loop (PLL) frequency synthesizer utilizing the Frequency Detector Method Speedup Circuit (FDMSC). FDMSC is composed of a Frequency Detector (FD) and a Charge Controller (CC). By CC, the control voltage of Voltage Controlled Oscillator (VCO) is forced to move to the objective value, and once the objective frequency is detected by FD, FDMSC can suppress the transient response of a PLL frequency synthesizer. The effectiveness of the proposed PLL frequency synthesizer is shown through some experiments., I E E E
Proc. IEEE International Conference on Consumer Electronics, Chicago, USA, 1997年06月
A novel (N+1/2) pulse swallow divider for the PLL frequency synthesizer
Y. Sumi; Y. Tanimoto; K. Tsuda; S. Obote; K. Syoubu; Y. Fukui
Proc. 1st Analog VLSI Workshop, Columbus, Ohio, USA, 1997年05月
A new lowpass filter for the fast frequency acquisition of the PLL frequency synthesizer
Y. Sumi; S. Obote; K. Tsuda; K. Syoubu; Y. Fukui
Proc. 1st Analog VLSI Workshop, Columbus, Ohio, USA, 1997年05月
PLL Frequency Synthesizer for Low Power ConsumptionY. Sumi; K. Syoubu; K. Tsuda; S. Obote; and Y. Fukui, In this paper, in order to achieve the low power consumption of programmable divider in a PLL frequency synthesizer, we propose a new prescaler method for low power consumption. A fixed prescaler is inserted in front of the (N + 1/2) programmable divider which is designed based on the new principle. The divider ratio in the loop does not vary at all even if such a prescaler is utilized. Then the permissible delay periods of a programmable divider can be extended to two times as long as the conventional method, and the low power consumption and low cost in a PLL frequency synthesizer have been achieved., IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
IEICE Transaction on Fundamentals of Electronics, Communications and Computer Sciences, 1997年03月
Novel fractional-N PLL frequency synthesizer with reduced phase errorY. Sumi; S. Obote; K. Tsuda; K. Syoubu; and Y. Fukui, Conventionally, the division ratio of the programmable divider in the Phase Locked Loop (PLL) frequency synthesizer is an only integer. Therefore, it has been hoped to realize the fractional-N programmable divider which can divide not only an integer step but also a fractional step.
In this paper, a new fractional-N programmable divider for the PLL frequency synthesizer is proposed. In this divider, the width of phase error pulse which phase detector produces in every period of reference frequency is decreased by introducing the new division ratio (N+1/2) besides N and (N+1)., I E E E
Proc. Asia Pacific Conference on Circuits and Systems (APCCAS), Seoul, Korea, 1996年11月
PLL frequency synthesizer with hidden prescaler
Y. Sumi; K. Syoubu; K. Tsuda; S. Obote; Y. Fukui
Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Seoul, Korea, 1996年07月
New speedup method of lock up time in the PLL frequency synthesizer
Y. Sumi; S. Obote; K. Tsuda; K. Syoubu; Y. Fukui
Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Seoul, Korea, 1996年07月
Phase error-less fractional (N+1/2) divider
Y. Sumi; K. Tsuda; S. Obote; K. Syoubu; Y. Fukui
Proc. International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Seoul, Korea, 1996年07月
